1. Field of the Invention
The present invention relates to computer arithmetic, and more particularly to calculating the expression A-sign(A) for signed binary integers.
2. Description of Related Art
The Moving Picture Experts Group (MPEG) standard has emerged as the dominant standard for compressed digital video. The MPEG-1 standard specifies a compressed video bit-stream rate of approximately 1.5 megabits per second, and a compressed stereo audio bit-stream rate of approximately 250 kilobits per second. The second standard, MPEG-2, will specify compression rates for higher-bandwidth distribution media, and is in the process of being formalized. To meet the MPEG standard, video and audio compression and decompression products must rapidly process the various algorithms used to implement the MPEG standard.
In MPEG video signal processing, the basic video information processing unit is typically a macro-block, which has a 16.times.16 pixel matrix comprising four 8.times.8 luminance blocks, and two 8.times.8 chrominance blocks. Each pixel in a luminance block or chrominance block has an output corresponding to an unsigned integer number, and each macro-block is part of a much larger luminance or chrominance frame, as the case may be.
MPEG video signal processing includes a computation requirement for calculating A-sign(A) for each pixel in a block, where A is a signed binary integer, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero.
FIG. 1 is a flow chart of algorithm 100, which is known, for calculating A-sign(A). At step 102, signed binary operand A is obtained. Decision step 104 tests whether A is zero. If A is zero, the algorithm branches to end step 112 since A provides A-sign(A). If A is nonzero, the algorithm branches to decision step 106 which tests whether A is negative. If A is negative, at step 108 A is incremented to obtain A+1, and the algorithm terminates at end step 112 since A+1 provides A-sign(A). Returning to decision step 106, if A is nonnegative (and therefore greater than zero since A is nonzero) then at step 110 A is decremented to obtain A-1, and the algorithm terminates at end step 112 since A-1 provides A-sign(A). Conventional variations to algorithm 100 are apparent. For instance, A can be tested for being negative before A is tested for being zero. Although algorithm 100 and related variations are simple to implement, they normally require several instruction cycles.
Moreover, providing zero detect at decision step 104 may require a large amount of chip area or several instruction cycles using conventional approaches. For instance, zero detect of an n-bit operand can be provided by an n-bit OR gate coupled to an inverter. The OR gate outputs a zero, which the inverter converts to a one, only when the operand consists of zero's. Drawbacks to this approach include the increased fan-in of the OR gate, which increases chip area, and the delay associated with ORing each bit of the operand. Another known technique for zero detect of a binary operand includes serially right-shifting the operand, and inspecting the shifted-outbits one at a time. As soon as a shifted-outbit of one is detected then the operand must be nonzero, whereas if all shifted-out bits are zero's then the operand must be zero. A drawback to this approach is that the right-shifting operation can be relatively time consuming and particularly difficult to implement in a single instruction cycle.
Accordingly, a need exists for calculating A-sign(A) in a rapid and efficient manner.